1. Field of the Invention
The present invention relates to a system and method for facilitating analysis of the performance of a portion of a data processing system.
2. Description of the Prior Art
It is known to trace the activity of a data processing system in order to obtain data representing activities of the data processing system that are desired to be monitored. Tracing mechanisms to produce trace streams of data representing such activities of the data processing system may be provided externally to the chip containing the processor core of the data processing system, or on-chip. However, with the general move towards more deeply embedded processor cores, it becomes more difficult to track the state of the processor core via externally accessible pins, and accordingly increased amounts of tracing functionality are being placed on-chip. An example of such on-chip tracing mechanisms is the Embedded Trace Macrocell (ETM) provided by ARM Limited, Cambridge, England, in association with various of their ARM processors.
Such tracing mechanisms produce in real time a trace stream of data representing activities of the data processing system that are desired to be traced, and such trace streams can provide accurate information about the performance of the data processing system. The trace stream can, for example, provide information about how long the processor core took to execute each instruction. However, what it cannot do, in general, is give an explanation of the source of any delays in the data processing system giving rise to performance problems.
An alternative technique for analysing the performance of a data processing system is to build a software simulation of the data processing system, using a simulator, for example the “ARMulator” product produced by ARM Limited. The running of such a software simulation can give very detailed information about the data processing system, but it is difficult to build an accurate simulation of a complete data processing system. In particular, unless the full behaviour of all components of the data processing system is known, building such an accurate simulation is impossible. Even if all components are fully understood, the work involved in building such a software simulation of a real data processing system is considerable.
It is an object of the present invention to provide a technique for facilitating the derivation of performance information for a portion of a data processing system, so as to enable a better understanding of the source of delays in the data processing system.